SI5350C-B Datasheet, PDF (14/31 Pages) Silicon Laboratories – FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR

Si5350C-B
4.4.4. Output Enable (OEB_0, OEB_1, OEB_2)
Up to three output enable pins (OEB_0/1/2) are available on the Si5350C. Similar to the FS pins, each OEB pin
can be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0,
CLK3, and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4,
and CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the
pin forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its
full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is
configurable as disabled high, disabled low, or disabled in high-impedance.
OEB_0
0
1
Output State
CLK Enabled
CLK Disabled
OEB_1
0
1
Output State
CLK Enabled
CLK Disabled
OEB_2
0
1
Output State
CLK Enabled
CLK Disabled
Customizable OEB Control
OEB_0
OEB_1
OEB_2
CLK0
OEB
CLK1
OEB
CLK2
OEB
CLK3
OEB
CLK4
OEB
CLK5
OEB
CLK6
OEB
CLK7
OEB
Glitchless Output Enable
CLKx
OEBx
Clock starts on the
first leading edge
Clock continues until
cycle is complete
Figure 9. Example Configuration of a Pin-Controlled Output Enable
4.4.5. Loss Of Lock (LOLB)
A loss of lock pin (LOLB) is available to indicate the status of the synchronous clock outputs. The LOLB pin is set to
a high state when the synchronous clock outputs are locked to the clock input (CLKIN). This is the normal
operating state for the synchronous clocks. The LOLB pin will go low when the reference clock at the CLKIN input
is removed or if its frequency deviates by more than 2000 ppm from its defined center frequency. In this case, the
synchronous clocks will continue to free-run. An option to disable the synchronous output clocks during an LOLB
condition (LOLB pin = low) is available. This only affects the clock outputs that were designated as synchronous
clock outputs. An external pull up resistor (recommended 10 kohms) is needed on LOLB as it is an open-drain
signal, not a push-pull output.
4.5. Design Considerations
The Si5350C is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance.
4.5.1. Power Supply Decoupling/Filtering
The Si5350C has built-in power supply filtering circuitry to help keep the number of external components to a
minimum. All that is recommended is one 0.1 to 1.0 µF decoupling capacitor per power supply pin. This capacitor
should be mounted as close to the VDD and VDDO pins as possible without using vias.
4.5.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. Power supply sequencing for VDD and VDDOx requires that all VDDOx be
powered up either before or at the same time as VDD. Unused VDDOx pins should be tied to VDD.
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