SI5350C-B Datasheet, PDF (10/31 Pages) Silicon Laboratories – FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR

Si5350C-B
3. Functional Description
The architecture of the Si5350C generates up to eight non-integer-related frequencies in any combination of free-
running and/or synchronous clocks. A block diagram of both the 3-output and the 8-output versions are shown in
Figure 4. Free-running clocks are generated using the on-chip oscillator + PLL, and the clock input pin (CLKIN)
provides an external input reference for the synchronous clocks. Each MultiSynth^TM is configurable with two
frequencies (F1_x, F2_x). This allows a pin controlled glitchless frequency change at each output (CLK0 to CLK5).
10-MSOP ^VDD
XA
XB
CLKIN
PLL
OSC
A
PLL
B
P0
Control
Logic
VDD
GND
XA
XB
CLKIN
PLL
OSC
A
PLL
B
P0
P1
Control
P2
Logic
P3
VDDO
MultiSynth 0
F1_0
R0
F2_0
FS
MultiSynth 1
F1_1
R1
F2_1
FS
MultiSynth 2
F1_2
R2
F2_2
FS
MultiSynth 3
CLK0
CLK1
CLK2
20-QFN
MultiSynth 0
F1_0
R0
F2_0
FS
MultiSynth 1
F1_1
R1
F2_1
FS
MultiSynth 2
F1_2
R2
F2_2
FS
MultiSynth 3
F1_3
R3
F2_3
FS
MultiSynth 4
F1_4
R4
F2_4
FS
MultiSynth 5
F1_5
R5
F2_5
FS
MultiSynth 6
F1_6
R6
MultiSynth 7
F1_7
R7
VDDOA
CLK0
CLK1
VDDOB
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOD
CLK6
CLK7
GND
Figure 4. Block Diagrams of the Si5350C Devices with 3 and 8 outputs
10
Rev. 1.0