SI5350A-B Datasheet, PDF (13/29 Pages) Silicon Laboratories – FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR

Si5350A-B
Up to two frequency select pins are available on the Si5350A. Each of the frequency select pins can be linked to
any of the clock outputs as shown in Figure 8. For example, FS_0 can be linked to control clock frequency
selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and
CLK4. Any other combination is also possible. The frequency select feature is not available for CLKs 6 and 7.
The Si5350A uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock
always completes its last cycle before starting a new clock cycle of a different frequency.
FS_0 Output Frequency
0 F1_0, F1_3, F1_5
1 F2_0, F2_3, F2_5
FS_1 Output Frequency
0 F1_1, F1_2, F1_4
1 F2_1, F2_2, F2_4
Customizable FS Control
FS
MultiSynth 0
FS_0
FS
MultiSynth 1
FS
MultiSynth 2
FS
MultiSynth 3
FS_1
FS
MultiSynth 4
MultiSynth 5
FS
Cannot be controlled
by FS pins
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Glitchless Frequency Changes
New frequency starts
at its leading edge
Frequency_A
CLKx
Frequency_B
Frequency_A
Full cycle completes before
changing to a new frequency
Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS)
4.3.4. Output Enable (OEB_0, OEB_1, OEB_2)
Up to three output enable pins (OEB_0/1/2) are available on the Si5350A. Similar to the FS pins, each OEB pin can
be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0, CLK3,
and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4, and
CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the pin
forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its
full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is
configurable as disabled high, disabled low, or disabled in high-impedance.
OEB_0
0
1
Output State
CLK Enabled
CLK Disabled
OEB_1
0
1
Output State
CLK Enabled
CLK Disabled
OEB_2
0
1
Output State
CLK Enabled
CLK Disabled
Customizable OEB Control
OEB_0
OEB_1
OEB_2
CLK0
OEB
CLK1
OEB
CLK2
OEB
CLK3
OEB
CLK4
OEB
CLK5
OEB
CLK6
OEB
CLK7
OEB
Glitchless Output Enable
CLKx
OEBx
Clock starts on the
first leading edge
Clock continues until
cycle is complete
Figure 9. Example Configuration of a Pin-Controlled Output Enable
Rev. 1.0
13