SI5350A-B Datasheet, PDF (12/29 Pages) Silicon Laboratories – FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR

Si5350A-B
See “4.3.1. Spread Spectrum Enable (SSEN)” for details.
Center
Frequency
A m p litud e
Reduced
A m p litud e
and EMI
f_c
No Spread
Spectrum
f_c
Down Spread
Figure 6. Available Spread Spectrum Profiles
4.2.3. Invert/Non-Invert
By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to
invert any of the clock outputs is also available.
4.2.4. Output State When Disabled
There are up to three output enable pins configurable on the Si5350A as described in “4.3.4. Output Enable
(OEB_0, OEB_1, OEB_2)” . The output state when disabled for each of the outputs is configurable as output high,
output low, or high-impedance.
4.2.5. Powering Down Unused Outputs
Unused clock outputs can be completely powered down to conserve power.
4.3. Programmable Control Pins (P0–P4) Options
Up to five programmable control pins (P0-P4) are configurable allowing direct pin control of the following features:
4.3.1. Spread Spectrum Enable (SSEN)
An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with
spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient
method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.
4.3.2. Power Down (PDN)
An optional power down control pin allows a full shutdown of the Si5350A to minimize power consumption when its
output clocks are not being used. The Si5350A is in normal operation when the PDN pin is held low and is in power
down mode when held high. Power consumption when the device is in power down mode is indicated in Table 3 on
page 4.
4.3.3. Frequency Select (FS_0, FS_1)
The Si5350A offers the option of configuring up to two frequencies per clock output on CLK0-CLK5. This is a useful
feature for applications that need to support more than one clock rate on the same output. An example of this is
shown in Figure 7 where the FS pins selects which frequency is generated from the clock output: F1_0 is
generated when FS is set low, and F2_0 is generated when FS is set high.
FS0
Bit Level
0
1
Output Frequency Selected
F1_0: 74.25 MHz
F2_0:
74.25 _MHz
1.001
27 MHz
XA
XB
FS0
Si5350A ^CLK0
74.25 MHz
or
74.25 _MHz
1.001
Video
Processor
Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output
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Rev. 1.0