SI5350A-B Datasheet, PDF (10/29 Pages) Silicon Laboratories – FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR

Si5350A-B
3. Functional Description
The Si5350A’s synthesis architecture consists of two high-frequency PLLs in addition to one high-resolution
fractional MultiSynth^TM divider per output. A block diagram of both the 3-output and 8-output versions are shown in
Figure 4. This unique architecture allows the Si5350A to simultaneously generate up to eight independent, non-
integer-related frequencies. In addition, each MultiSynth^TM is configurable with two different frequencies (F1_x,
F2_x). This allows a pin controlled glitchless frequency change at each output (CLK0 to CLK5).
10-MSOP ^VDD
XA
PLL
OSC
A
XB
PLL
B
P0
Control
P1
Logic
VDD
GND
XA
PLL
OSC
A
XB
PLL
B
P0
P1
P2
Control
Logic
P3
P4
VDDO
MultiSynth 0
F1_0
R0
F2_0
FS
MultiSynth 1
F1_1
R1
F2_1
FS
MultiSynth 2
F1_2
R2
F2_2
FS
MultiSynth 3
CLK0
CLK1
CLK2
20-QFN
MultiSynth 0
F1_0
R0
F2_0
FS
MultiSynth 1
F1_1
R1
F2_1
FS
MultiSynth 2
F1_2
R2
F2_2
FS
MultiSynth 3
F1_3
R3
F2_3
FS
MultiSynth 4
F1_4
R4
F2_4
FS
MultiSynth 5
F1_5
R5
F2_5
FS
MultiSynth 6
F1_6
R6
MultiSynth 7
F1_7
R7
VDDOA
CLK0
CLK1
VDDOB
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOD
CLK6
CLK7
GND
Figure 4. Block Diagrams of 3-Output and 8-Output Si5350A Devices
10
Rev. 1.0