S-93C46A Datasheet, PDF (8/53 Pages) Seiko Instruments Inc – CMOS SERIAL E2PROM

CMOS SERIAL E²PROM
S-93C46A/56A/66A
CS
SK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
24 25 26 27 28 29
40 41 42 43 44 45
DI
DO
1
1
0 A7 A6 A5 A4 A3 A2 A1 A0
Hi-Z
0 D15 D14 D13
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15 D14 D13
Hi-Z
A7A6A5A4A3A2A1A0+1
Figure 6 Read Timing (S-93C66A)
A7A6A5A4A3A2A1A0+2
2. Write (WRITE, ERASE, WRAL, ERAL)
There are four write instructions, WRITE, ERASE, WRAL, and ERAL. Each automatically begins writing to the non-
volatile memory when CS goes low at the completion of the specified clock input.
The write operation is completed in 10 ms (t_PR Max.), and the typical write period is less than 5 ms. In the S-
93C46A/56A/66A, it is easy to VERIFY the completion of the write operation in order to minimize the write cycle by setting
CS to high and checking the DO pin, which is low during the write operation and high after its completion. This VERIFY
procedure can be executed over and over again.
Because all SK and DI inputs are ignored during the write operation, any input of instruction will also be disregarded.
When DO outputs high after completion of the write operation or if it is in the high-impedence state (Hi-Z), the input of
instructions is available. Even if the DO pin remains high, it will enter the high-impedence state upon the recognition of a
high of DI (start-bit) attached to the rising edge of an SK pulse. (see Figure 3).
DI input should be low during the VERIFY procedure.
Seiko Instruments Inc.
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