S-93C46A Datasheet, PDF (14/53 Pages) Seiko Instruments Inc – CMOS SERIAL E2PROM

CMOS SERIAL E²PROM
S-93C46A/56A/66A
n Receiving a Start-Bit
Both the recognition of a start-bit and the VERIFY procedure occur when CS is “high”. Therefore, only after a write
operation, in order to accept the next command by having CS go high, the DO pin switch from a state of high-impedence to
a state of data output; but if it recognizes a start-bit, the DO pin returns to a state of high-impedence.
n Three-wire Interface (DI-DO direct connection)
Although the normal configuration of a serial interface is a 4-wire interface to CS, SK, DI, and DO, a 3-wire interface is
also a possibility by connecting DI and DO. However, since there is a possibility that the DO output from the serial memory
IC will interfere with the data output from the CPU with a 3-wire interface, install a resistor between DI and DO in order to
give preference to data output from the CPU to DI(See Figure 22).
CPU
S-93C46A/56A/66A
SIO
DI
DO
R : 10k ∼ 100kΩ
Figure 22
Seiko Instruments Inc.
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