S-93C46A Datasheet, PDF (7/53 Pages) Seiko Instruments Inc – CMOS SERIAL E2PROM

CMOS SERIAL E²PROM
S-93C46A/56A/66A
n Operation
Instructions (in the order of start-bit, instruction, address, and data) are latched to DI in synchronization with the rising
edge of SK after CS goes high. A start-bit can only be recognized when the high of DI is latched to the rising edge of SK
when CS goes from low to high, it is impossible for it to be recognized as long as DI is low, even if there are SK pulses after
CS goes high. Any SK pulses input while DI is low are called "dummy clocks." Dummy clocks can be used to adjust the
number of clock cycles needed by the serial IC to match those sent out by the CPU. Instruction input finishes when CS
goes low, where it must be low between commands during t_CDS.
All input, including DI and SK signals, is ignored while CS is low, which is stand-by mode.
1. Read
The READ instruction reads data from a specified address. After A0 is latched at the rising edge of SK, DO output
changes from a high-impedance state (Hi-Z) to low level output. Data is continuously output in synchronization with the rise
of SK.
When all of the data (D0) in the specified address has been read, the data in the next address can be read with the input
of another SK clock. Thus, it is possible for all of the data addresses to be read through the continuous input of SK clocks
as long as CS is high.
The last address (An ŸŸŸ A1 A0 = 1 ŸŸŸ 11) rolls over to the top address (An ŸŸŸ A1 A0 = 0 ŸŸŸ 00).
CS
SK
1 2 3 4 5 6 7 8 9 10 11 12
23 24 25 26 27 28
39 40 41 42 43 44
DI
DO
1
1
0 A5 A4 A3 A2 A1 A0
Hi-Z
0 D15 D14 D13
D2 D1 D0 D15 D14 D13
D2 D1 D0 D15 D14 D13
Hi-Z
A5A4A3A2A1A0+1
Figure 4 Read Timing (S-93C46A)
A5A4A3A2A1A0+2
CS
SK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
24 25 26 27 28 29
40 41 42 43 44 45
DI
DO
1
1
0 X A6 A5 A4 A3 A2 A1 A0
Hi-Z
0 D15 D14 D13
D2 D1 D0 D15 D14 D13
D1 D0 D15 D14 D13
Hi-Z
A6A5A4A3A2A1A0+1
Figure 5 Read Timing (S-93C56A)
A6A5A4A3A2A1A0+2
6
Seiko Instruments Inc.