S-93C46A Datasheet, PDF (35/53 Pages) Seiko Instruments Inc – CMOS SERIAL E2PROM

Collection of Product FAQs
Author: Kano Tomoo
Date: 98/11/12 (Thursday) 10:17 (modified: 99/01/13)
<Information level>
A:
Public (Printing)
Index:
D: Technical terms
<Product>
Division name: 01 IC
Category 1: 12 Memory
Category 2:
Cal. No.:
2. Serial EEPROM
Overall
Related documents:
Question:
What about the basic terms (Test pin, ORG pin)
Answer:
TEST pin
This is an input pin used to enter a test mode when tests are conducted during an SII inspection
process. This information is not provided to users. It can be used with a GND or Vcc connection, or in
an open state (see note). This is important in maintaining compatibility with the pin layouts of other
companies. Some users fear that the test mode may be inadvertently entered during operation, but such
fears are unnecessary, as a potential of at least 10 V must be constantly supplied to enter the test
mode.
(Note) Since the TEST pin has a C-MOS input structure, the GND or Vcc connection is most suited for
this pin.
ORG (Organization) pin
Input pin used to specify a memory configuration. A normal memory has a “16 bit/1 address” data
configuration and includes no ORG pin. Competing manufacturers, however, have released products
that enable data to be switched between “x16” and “x8” using “H” or “L” of the ORG pin. Since this
function is provided for the 93C series of the NS code, there is a compatibility problem. SII has not yet
released products featuring this function.
<Remarks>
FAQ No.: 12014
34