S-25A640A Datasheet, PDF (8/32 Pages) Seiko Instruments Inc – Function to prevent malfunction by monitoring clock pulse

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E²PROM
S-25A640A, S-25A640B
Rev.3.2_01
 AC Electrical Characteristics
1. S-25A640A
Table 18 Measurement Conditions
Input pulse voltage
Output reference voltage
Output load
0.2 × VCC to 0.8 × VCC
0.5 × VCC
100 pF
Table 19
Item
SCK clock frequency
Symbol
fSCK
Ta = −40°C to +125°C
VCC = 2.5 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 4.5 V to 5.5 V
Min. Max. Min. Max. Min. Max.
－
2.5
－
3.5
－
5.0
Unit
MHz
CS setup time during CS falling
tCSS.CL
120
－
90
－
90
－
ns
CS setup time during CS rising
tCSS.CH
120
－
90
－
90
－
ns
CS deselect time
tCDS
210
－
160
－
140
－
ns
CS hold time during CS falling
tCSH.CL
120
－
90
－
90
－
ns
CS hold time during CS rising
SCK clock time "H"^*1
SCK clock time "L"^*1
Rising time of SCK clock^*2
Falling time of SCK clock^*2
SI data input setup time
SI data input hold time
tCSH.CH
120
－
90
－
90
－
ns
tHIGH
160
－
125
－
95
－
ns
tLOW
160
－
125
－
95
－
ns
tRSK
－
1
－
1
－
1
μs
tFSK
－
1
－
1
－
1
μs
tDS
30
－
20
－
20
－
ns
tDH
40
－
30
－
30
－
ns
SCK "L" hold time during HOLD rising
tSKH.HH
90
－
70
－
70
－
ns
SCK "L" hold time during HOLD falling
tSKH.HL
50
－
40
－
40
－
ns
SCK "L" setup time during HOLD falling
tSKS.HL
0
－
0
－
0
－
ns
SCK "L" setup time during HOLD rising
Disable time of SO output^*2
Delay time of SO output
Hold time of SO output
Rising time of SO output^*2
Falling time of SO output^*2
tSKS.HH
0
－
0
－
0
－
ns
tOZ
－
130
－
100
－
100 ns
tOD
－
160
－
120
－
90 ns
tOH
0
－
0
－
0
－
ns
tRO
－
110
－
80
－
80 ns
tFO
－
110
－
80
－
80 ns
Disable time of SO output during HOLD falling^{*2 t}OZ.HL
－
130
－
100
－
100 ns
Delay time of SO output during HOLD rising^{*2 t}OD.HH
－
110
－
80
－
80 ns
WP setup time
tWS1
0
－
0
－
0
－
ns
WP hold time
tWH1
0
－
0
－
0
－
ns
WP release / setup time
tWS2
0
－
0
－
0
－
ns
WP release / hold time
tWH2
200
－
150
－
150
－
ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK μs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) + tHIGH (min.) by
minimizing the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
Item
Write time
Table 20
Ta = −40°C to +125°C
Symbol
VCC = 2.5 V to 5.5 V
Unit
Min.
Max.
tPR
－
4.0
ms
8