S-25A640A Datasheet, PDF (19/32 Pages) Seiko Instruments Inc – Function to prevent malfunction by monitoring clock pulse

Rev.3.2_01
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E²PROM
S-25A640A, S-25A640B
CS
WP
SCK
SI
High / Low
1 2 3 4 5 6 7 8 9 10 11 22 23 24 25 26 27 28 29 30 31 32
Instruction
16-bit Address (n)
Data Byte (n)
Data Byte (n + x)
A15 A14 A13 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
D4 D3 D2 D1 D0
High-Z
SO
Remark The higher addresses A15 to A13 = Don't care.
Figure 18 WRITE Operation (Page)
 Protect Operation
Table 25 shows the block settings of write protect. Table 26 shows the protect operation for this IC. As long as bit SRWD,
the Status Register Write Disable bit, in the status register is reset to "0" (it is in reset before the shipment), the value of
status register can be changed.
These are two statues when bit SRWD is set to "1".
• Write in the status register is possible; write protect ( WP ) is in "H".
• Write in the status register is impossible; write protect ( WP ) is in "L". Therefore the write protect area which is set
by protect bit (BP1, BP0) in the status register cannot be changed.
These operations are to set Hardware Protect (HPM).
• After setting bit SRWD, set write protect ( WP ) to "L".
• Set bit SRWD completed setting write protect ( WP ) to "L".
The timing during the cycle write to the status register is showed in "Figure 8 Valid Timing in Write Protect" and
"Figure 9 Invalid Timing in Write Protect".
By inputting "H" to write protect ( WP ), Hardware Protect (HPM) is released. If the write protect ( WP ) is "H", Hardware
Protect (HPM) does not function, Software Protect (SPM) which is set by the protect bits in the status register (BP1, BP0)
only works.
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