S-25A640A Datasheet, PDF (16/32 Pages) Seiko Instruments Inc – Function to prevent malfunction by monitoring clock pulse

FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E²PROM
S-25A640A, S-25A640B
Rev.3.2_01
4. Read the status register (RDSR)
Reading data in the status register is possible by the RDSR instruction. During the write operation, it is possible to
confirm the progress by checking bit WIP.
Set the chip select ( CS ) "L" first. After that, input the instruction code from serial data input (SI). The status of bit in
the status register is output from serial data output (SO). Sequential read is available for the status register. To stop
the read cycle, set CS to "H".
It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the write
cycle.
The 2 bits WEL and WIP are updated during the write cycle. The updated nonvolatile bits SRWD, BP1 and BP0 can
be acquired by performing a new RDSR instruction after verifying the completion of the write cycle.
CS
WP
High / Low
SCK
SI
SO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Instruction
High-Z
Outputs Data in the Status Register
b7 b6 b5 b4 b3 b2 b1 b0 b7
Figure 14 RDSR Operation
5. Write in the status register (WRSR)
The values of status register (SRWD, BP1, BP0) can be rewritten by inputting the WRSR instruction. But b6, b5, b4,
b1, b0 of status register cannot be rewritten. b6 to 4 are always data "0" when reading the status register.
Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown
below.
Set the chip select ( CS ) "L" first. After that, input the instruction code and data from serial data input (SI). To start
WRSR write (tPR), set the chip select ( CS ) to "H" after inputting data or before inputting a rising of the next serial
clock. It is possible to confirm the operation status by reading the value of bit WIP during WRSR write. Bit WIP is "1"
during write, "0" during any other status. Bit WEL is reset when write is completed.
With the WRSR instruction, the values of BP1 and BP0; which determine the area size the users can handle as the
read only memory; can be changed. Besides bit SRWD can be set or reset by the WRSR instruction depending on
the status of write protect ( WP ). With a combination of bit SRWD and write protect ( WP ), this IC can be set in
Hardware Protect mode (HPM). In this case, the WRSR instruction is not be performed (Refer to " Protect
Operation").
Bit SRWD and BP1, BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction.
The newly updated value is changed when the WRSR instruction has completed.
To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clock) while CS is in "L".
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