S-34C04A Datasheet, PDF (7/22 Pages) Seiko Instruments Inc – FOR DIMM SERIAL PRESENCE DETECT

Rev.1.0_01_U
2-WIRE SERIAL E²PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C04A
 Pin Functions
1. VDD (Power supply) pin
The VDD pin is used to apply positive supply voltage. Regarding the applied voltage value, refer to
" Recommended Operation Conditions". Set a bypass capacitor of about 0.1 μF between the VDD pin and the
VSS pin for stabilization as close to IC as possible.
2. SA0, SA1 and SA2 (Select address input) pins
In this IC, to set the slave address, connect each of the SA0 pin, SA1 pin and SA2 pin to the VSS pin or the VDD pin.
Therefore the users can set 8 types of slave address by a combination of the SA0 pin, SA1 pin, SA2 pin.
Comparing the slave address transmitted from the master device and one that you set, makes possible to select one
slave address from other devices connected onto the bus.
Each of the SA0 pin, SA1 pin and SA2 pin has a built-in pull-down resistor. In open, the pin is set to the same status
as it connected to the VSS pin.
The SA0 pin is used to detect the VHV voltage, when decoding an SWPn or CWP instruction. Refer to Table 10 for pin
setting and device select code.
3. SDA (Serial data I/O) pin
The SDA pin is used for the bi-directional transmission of serial data. This pin is a signal input pin, and an Nch
open-drain output pin.
In use, generally, connect the SDA line to any other device which has the open-drain or open-collector output with
Wired-OR connection by pulling up to VDD by a resistor.
4. SCL (Serial clock input) pin
The SCL pin is used for the serial clock input. Since the signals are processed at a rising or falling edge of the SCL
clock, pay attention to the rising and falling time and comply with the specification.
 Initial Delivery State
Initial delivery state of all address is "FFh". All write protects are cleared.
 Operation
This IC behaves as a slave device in the 2-wire I²C-bus protocol.
All operations are synchronized by the serial clock. Read and write operations are initiated by a start condition, generated
by the master device. The start condition is followed by a device select code and read / write bit, and this IC generates an
acknowledge bit.
The 7-bit device select code is constructed of 4-bit device type identifier code (DTIC) and 3-bit code which shows the
state of the SA0 pin, SA1 pin, and SA2 pin. DTIC is a code to define functions.
When writing data to this IC, this IC generates an acknowledge bit during the 9th bit time, following the master device's
8-bit transmission. When data is read by the master device, the master device acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by a master device which generates stop condition after an acknowledge
for write, and after no acknowledge for read.
This IC has the timeout function. This IC shall not initiate clock stretching, which is an optional I²C-bus feature.
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