S-34C04A Datasheet, PDF (17/22 Pages) Seiko Instruments Inc – FOR DIMM SERIAL PRESENCE DETECT

Rev.1.0_01_U
2-WIRE SERIAL E²PROM FOR DIMM SERIAL PRESENCE DETECT
S-34C04A
2. 2 Random read
Random read is used to read the data at an arbitrary memory address.
A dummy write is performed to load the memory address into the address counter.
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "0" following a start
condition, it responds with an acknowledge.
This IC then receives an 8-bit word address and responds with an acknowledge. The memory address is loaded
to the address counter in this IC by these operations. Reception of write data does not follow in a dummy write
whereas reception of write data follows in byte write and in page write.
Since the memory address is loaded into the memory address counter by dummy write, the master device can
read the data starting from the arbitrary memory address by transmitting a new start condition and performing the
same operation in the current address read.
That is, when this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "1", following a
start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted from this IC synchronously
with the SCL clock. The master device outputs stop condition not an acknowledge, the reading of this IC is ended.
SDA
LINE
S
W
T
R
A
I
S
T
A
R
E
NO ACK from
Master Device
S
T
R
DEVICE
T
T SELECT CODE ^E
WORD ADDRESS (n)
R
DEVICE
A
T SELECT CODE ^D
DATA
O
P
1 0 1 0 SA2 SA1 SA0 0 _{W7 W6 W5 W4 W3 W2 W1 W0}
1 0 1 0 SA2 SA1 SA0 1 D7 D6 D5 D4 D3 D2 D1 D0
M
LR A
S
S/ C
B
BW K
AM
CS
KB
LR A
S/ C
BW K
ADR INC
DUMMY WRITE
Figure 13 Random Read
2. 3 Sequential read
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "1" following a start
condition both in current address read and random read, it responds with an acknowledge.
When an 8-bit data is output from this IC synchronously with the SCL clock, the address counter is automatically
incremented.
When the master device responds with an acknowledge, the data at the next memory address is transmitted.
Response with an acknowledge by the master device has the memory address counter in this IC incremented and
makes it possible to read data in succession. This is called sequential read.
The master device outputs stop condition not an acknowledge, the reading of this IC is ended.
Data can be read in succession in the sequential read mode. When the memory address counter reaches the last
word address, it rolls over to the first word address of same page address.
R
E
DEVICE A
SELECT CODE D
SDA
LINE
1 D7
RA
/C
WK
NO ACK from
Master Device
S
A
A
A
T
C
C
C
O
K
K
K
P
D0 D7
D0 D7
D0 D7
D0
DATA (n)
DATA (n + 1)
DATA (n + 2)
DATA (n + x)
ADR INC
ADR INC
ADR INC
ADR INC
Figure 14 Sequential Read
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