S-19500A03A-E8T1U4 Datasheet, PDF (28/52 Pages) Seiko Instruments Inc – CMOS VOLTAGE REGULATOR WITH WATCHDOG TIMER AND RESET FUNCTION

FOR AUTOMOTIVE 125°C OPERATION HIGH-WITHSTAND VOLTAGE CMOS VOLTAGE REGULATOR WITH WATCHDOG TIMER AND RESET FUNCTION
S-19500/19501 Series
Rev.1.2_01
2. Detector block
2. 1 Basic operation
(1) When the output voltage (VOUT) of the regulator is release voltage (+VDET) of the detector or higher, the Nch
transistor (N1 and N2) are turned off and "H" is output to the RO pin. Since the Pch transistor (P1) is turned on,
the input voltage to the comparator (C1) is
RB • VOUT
RA + RB
.
(2) Even if VOUT decreases to +VDET or lower, "H" is output to the RO pin when VOUT is the detection voltage (−VDET)
or higher. When VOUT decreases to −VDET (point A in Figure 41) or lower, N1 which is controlled by C1 is turned
on, and CDLY is discharged. If the DLY pin voltage (VDLY) decreases to the lower reset timing threshold voltage
(VDRL) or lower, N2 of output stage of C2 is turned on, and then "L" is output to the RO pin. At this time, P1 is
turned off, and the input voltage to C1 is
RB
RA +
• VOUT
RB + RC
.
(3) If VOUT further decreases to the IC's minimum operation voltage or lower, the RO pin output is "H".
(4) When VOUT increases to the IC's minimum operation voltage or higher, "L" is output to the RO pin. Moreover,
even if VOUT exceeds −VDET, the output is "L" when VOUT is lower than +VDET.
(5) When VOUT increases to +VDET (point B in Figure 41) or higher, N1 is turned off and CDLY is charged. N2 is
turned off if VDLY increases to the upper timing threshold voltage (VDU) or higher, and "H" is output to the RO pin.
VOUT
R_C
P1
R_A
Reference
voltage circuit _RB
C1
+
−
N1
C2
RO
−
+
N2
VSS
DLY
C_DLY
Figure 40 Operation of Detector Block
(1) (2) (3) (4)
B
Hysteresis width
A
(V_HYS)
(5)
V_OUT
Release voltage (+V_DET)
Detection voltage (−V_DET)
Minimum operation voltage
V_SS
VOUT
RO pin output
VSS
t_rd
Figure 41 Timing Chart of Detector Block
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