S-19500A03A-E8T1U4 Datasheet, PDF (23/52 Pages) Seiko Instruments Inc – CMOS VOLTAGE REGULATOR WITH WATCHDOG TIMER AND RESET FUNCTION

FOR AUTOMOTIVE 125°C OPERATION HIGH-WITHSTAND VOLTAGE CMOS VOLTAGE REGULATOR WITH WATCHDOG TIMER AND RESET FUNCTION
Rev.1.2_01
S-19500/19501 Series
2. Detector block
2. 1 Detection voltage (−VDET)
The detection voltage is a voltage at which the output of the RO pin turns to "L". The detection voltage varies
slightly among products of the same specification. The variation of detection voltage between the specified
minimum (−VDET min.) and the maximum (−VDET max.) is called the detection voltage range (Refer to Figure 34).
2. 2 Release voltage (+VDET)
The release voltage is a voltage at which the output of the RO pin turns to "H". The release voltage varies slightly
among products of the same specification. The variation of release voltage between the specified minimum (+VDET
min.) and the maximum (+VDET max.) is called the release voltage range (Refer to Figure 35). This value is
calculated from the actual detection voltage (−VDET) of a product and the hysteresis width (VHYS), and is +VDET =
−VDET + VHYS.
V_OUT
−V_DET max.
−V_DET min.
Detection voltage
Detection voltage
range
Release voltage
+V_DET max.
+V_DET min.
V_OUT
Release voltage
range
V_RO
V_RO
Release delay time
Figure 34 Detection Voltage
Figure 35 Release Voltage
2. 3 Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage and the release voltage. Setting the
hysteresis width between the detection voltage and the release voltage prevents malfunction caused by noise on
the VOUT pin voltage (VOUT).
2. 4 Release delay time (trd)
The release delay time is the time period from when VOUT exceeds the release voltage (+VDET) to when the RO pin
output inverts (Refer to Figure 36), and this value changes according to the delay time adjustment capacitor
(CDLY). trd is determined by a built-in constant current which charges CDLY, the charge detection threshold of the
DLY pin, and the capacitance of CDLY. It is calculated by using the following equation.
trd = CDLY ×
VDU
ID,cha
V
V_OUT
+V_DET
V_DU
V_DLY
VRO
t
t_rd
Figure 36 Release Delay Time
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