S-19500A03A-E8T1U4 Datasheet, PDF (26/52 Pages) Seiko Instruments Inc – CMOS VOLTAGE REGULATOR WITH WATCHDOG TIMER AND RESET FUNCTION

FOR AUTOMOTIVE 125°C OPERATION HIGH-WITHSTAND VOLTAGE CMOS VOLTAGE REGULATOR WITH WATCHDOG TIMER AND RESET FUNCTION
S-19500/19501 Series
Rev.1.2_01
 Operation
1. Regulator block
1. 1 Basic operation
Figure 39 shows the block diagram of the regulator in the S-19500/19501 Series.
The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output voltage
resistance-divided by feedback resistors (Rs and Rf). It supplies the gate voltage necessary to maintain the
constant output voltage which is not influenced by the input voltage and temperature change, to the output
transistor.
VIN
Current
supply
V_ref
Error
amplifier
−
+
Reference voltage
circuit
*1
R_f
V_fb
R_s
VOUT
VSS
*1. Parasitic diode
Figure 39
1. 2 Output transistor
In the S-19500/19501 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due to
reverse current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential of VOUT
became higher than VIN.
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