S-19500A03A-E8T1U4 Datasheet, PDF (20/52 Pages) Seiko Instruments Inc – CMOS VOLTAGE REGULATOR WITH WATCHDOG TIMER AND RESET FUNCTION

FOR AUTOMOTIVE 125°C OPERATION HIGH-WITHSTAND VOLTAGE CMOS VOLTAGE REGULATOR WITH WATCHDOG TIMER AND RESET FUNCTION
S-19500/19501 Series
Rev.1.2_01
 Selection of Delay Time Adjustment Capacitor (CDLY)
In the S-19500/19501 Series, the delay time adjustment capacitor (CDLY) is necessary between the DLY pin and the
VSS pin to adjust the release delay time (trd) of the detector and the monitoring time of the watchdog timer.
The set release delay time (trd(S)), the set watchdog trigger time (tWI,tr(S)), the set watchdog output "L" time (tWD,l(S)) and
the set watchdog output pulse period (tWD,p(S)) are calculated by using following equations, respectively.
The release delay time (trd), the watchdog trigger time (tWI,tr), the watchdog output "L" time (tWD,l) and the watchdog
output pulse period (tWD,p) at the time of the condition of CDLY = 47 nF are shown in " Electrical Characteristics".
trd(S) [ms] = trd [ms] ×
CDLY [nF]
47 [nF]
tWI,tr(S) [ms] = tWI,tr [ms] ×
CDLY [nF]
47 [nF]
tWD,l(S) [ms] = tWD,l [ms] ×
CDLY [nF]
47 [nF]
tWD,p(S) [ms] = tWI,tr(S) [ms] + tWD,l(S) [ms]
Caution 1. The above equations will not guarantee successful operation. Perform thorough evaluation including
the temperature characteristics using an actual application to set the constants.
2. Mounted board layout should be made in such a way that no current flows into or flows from the DLY
pin since the impedance of the DLY pin is high, otherwise correct delay time and monitoring time may
not be provided.
3. Select CDLY whose leakage current can be ignored against the built-in constant current. The leakage
current may cause deviation in delay time and monitoring time. When the leakage current is larger
than the built-in constant current, no release takes place.
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