S-24C02DI-J8T1U5 Datasheet, PDF (25/47 Pages) Seiko Instruments Inc – Write protect function during low power supply voltage

Rev.3.0_01_U
2-WIRE SERIAL E²PROM
S-24C02D/04D/08D16D
7. Data hold time (tHD.DAT = 0 ns)
If SCL and SDA of this IC are changed at the same time, it is necessary to prevent a start / stop condition from being
mistakenly recognized due to the effect of noise.
This IC may error if it does not recognize a start / stop condition correctly during transmission.
In this IC, it is recommended to set the delay time of 0.3 μs minimum from a falling edge of SCL for the SDA.
This is to prevent this IC from going in a start / stop condition due to the time lag caused by the load of the bus line.
t_HD.DAT = 0.3 μs min.
SCL
SDA
Figure 24 Data Hold Time
8. SDA pin and SCL pin noise suppression time
This IC includes a built-in low-pass filter at the SDA pin and the SCL pin to suppress noise. If the power supply
voltage is 5.0 V, this suppression time can be suppressed noise with a pulse width of approx. 80 ns.
For details of the assurable value, refer to noise suppression time (tl) in Table 10 in " AC Electrical
Characteristics".
300
Noise suppression time
(t_I) max.
200
[ns]
100
2
3
4
5
Power supply voltage (V_CC)
[V]
Figure 25 Noise Suppression Time for SDA Pin and SCL Pin
25