S-24C02DI-J8T1U5 Datasheet, PDF (18/47 Pages) Seiko Instruments Inc – Write protect function during low power supply voltage

2-WIRE SERIAL E²PROM
S-24C02D/04D/08D16D
Rev.3.0_01_U
8. Read
8. 1 Current address read
Either in writing or in reading this IC holds the last accessed memory address. The memory address is maintained
when the instruction transmission is not interrupted, and the memory address is maintained as long as the power
voltage does not decrease less than the operating voltage.
The master device can read the data at the memory address of the current address pointer without assigning the
word address as a result, when it recognizes the position of the address pointer in this IC. This is called "Current
Address Read".
In the following the address counter in this IC is assumed to be "n".
When this IC receives a 7-bit device address and a 1-bit read / write instruction code set to "1" following a start
condition, it responds with an acknowledge.
Next an 8-bit data at the address "n" is sent from this IC synchronous to the SCL clock. The address counter is
incremented and the content of the address counter becomes n + 1. The master device outputs stop condition not
an acknowledge, the reading of this IC is ended.
S
T
R
E
NO ACK from
Master Device
S
T
A
A
O
R
D
P
T
DEVICE
ADDRESS
DATA
SDA LINE
1 0 1 0 A2 A1 A0 1
D7 D6 D5 D4 D3 D2 D1 D0
M
LR A
S
S/ C
B
BW K
Remark In the S-24C04D/08D/16D, A0 = Don't care.
In the S-24C08D/16D, A1 = Don't care.
In the S-24C16D, A2 = Don't care.
Set A0, A1, A2 to "0" in the product with SOT-23-5 package.
Figure 13 Current Address Read
Attention should be paid to the following point on the recognition of the address pointer in this IC.
In Read, the memory address counter in this IC is automatically incremented after output of the 8th bit of the data.
In Write, on the other hand, the higher bits of the memory address (the higher bits of the word address and the
page address^*1) are left unchanged and are not incremented.
∗_{1. In the S-24C02D, the higher 5 bits (W7 to W3) of the word address.}
In the S-24C04D, the higher 4 bits (W7 to W4) of the word address and the page address (P0).
In the S-24C08D, the higher 4 bits (W7 to W4) of the word address and the page address (P1, P0).
In the S-24C16D, the higher 4bits (W7 to W4) of the word address and the page address (P2, P1, P0).
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