S93A46A Datasheet, PDF (16/41 Pages) Seiko Instruments Inc – 125C OPERATION 3-WIRE SERIAL

125°C OPERATION 3-WIRE SERIAL E²PROM FOR AUTOMOTIVE
S-93A46A/56A/66A
Rev.6.1_00
4. 5 Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and then input the
ERAL instruction and an address following the start bit. Any address can be input. There is no need to input
data. The chips erase operation starts when CS goes low. When the clocks more than the specified number
have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For details of the clock pulse
monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”.
CS
t CDS
SK
1
2
3
4
5
6
7
89
Verify
Standby
DI
<1> 0
010
DO
High-Z
4Xs
t SV
t HZ1
Busy _Ready
High-Z
t PR
Figure 14 Chip Erase Timing (S-93A46A)
CS
t CDS
SK
1
2
3
4
5
6
7
8 9 10 11
Verify
Standby
DI
<1> 0
010
High-Z
6Xs
DO
t SV
Busy _Ready
t PR
t HZ1
High-Z
Figure 15 Chip Erase Timing (S-93A56A, S-93A66A)
16
Seiko Instruments Inc.