S93A46A Datasheet, PDF (12/41 Pages) Seiko Instruments Inc – 125C OPERATION 3-WIRE SERIAL

125°C OPERATION 3-WIRE SERIAL E²PROM FOR AUTOMOTIVE
S-93A46A/56A/66A
Rev.6.1_00
4. Writing (WRITE, ERASE, WRAL, ERAL)
A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write (WRAL), and
chip erase (ERAL).
A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when a low level is
input to CS after a specified number of clocks have been input. The SK and DI inputs are invalid during the write
period, so do not input an instruction.
Input an instruction while the output status of the DO pin is high or high impedance (High-Z).
A write operation is valid only in program enable mode (refer to “5. Write enable (EWEN) and write disable
(EWDS)”).
4. 1 Verify operation
A write operation executed by any instruction is completed within 8 ms (write time t_PR: typically 4 ms), so if the
completion of the write operation is recognized, the write cycle can be minimized. A sequential operation to
confirm the status of a write operation is called a verify operation.
(1) Operation
After the write operation has started (CS = low), the status of the write operation can be verified by confirming
the output status of the DO pin by inputting a high level to CS again. This sequence is called a verify
operation, and the period that a high level is input to the CS pin after the write operation has started is called
the verify operation period.
The relationship between the output status of the DO pin and the write operation during the verify operation
period is as follows.
• DO pin = low: Writing in progress (busy)
• DO pin = high: Writing completed (ready)
(2) Operation example
There are two methods to perform a verify operation: Waiting for a change in the output status of the DO pin
while keeping CS high, or suspending the verify operation (CS = low) once and then performing it again to
verify the output status of the DO pin. The latter method allows the CPU to perform other processing during
the wait period, allowing an efficient system to be designed.
Caution 1. Input a low level to the DI pin during a verify operation.
2. If a high level is input to the DI pin at the rise of SK when the output status of the DO pin is
high, the S-93A46A/56A/66A latches the instruction assuming that a start bit has been input.
In this case, note that the DO pin immediately enters a high-impedance (High-Z) state.
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