S-8215AAA-K8T2U Datasheet, PDF (12/29 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK

BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.3_02
4. Test mode
The overcharge detection delay time (t_CU) can be shortened by entering the test mode.
The test mode can be set by retaining the VDD pin voltage 5.0 V or more higher than the VC1 pin voltage for the
transition time to test mode (t_TST) or longer. The status is retained by the internal latch and the test mode is retained
even if the VDD pin voltage is decreased to the same voltage as that of the VC1 pin voltage.
After that, the latch for retaining the test mode is reset and the S-8215A Series exits from test mode under the
overcharge status.
VDD pin voltage
VC1 pin voltage
Pin voltage
5.0 V or
more
V_CUn
Battery voltage
(n = 1 to 5)
V_HCn
Test mode
t_TST = 80 ms max.
CO pin
(Active "H")
CO pin
(Active "L")
32 ms typ.
2.0 ms typ.
Figure 10
Caution
1. When the VDD pin voltage is decreased to lower than the UVLO voltage of 2 V typ., the
S-8215A Series exits from test mode.
2. Set the test mode when no batteries are overcharged.
3. The overcharge timer reset delay time (t_TR) is not shortened in the test mode.
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