HYM322030S Datasheet, PDF (9/9 Pages) Siemens Semiconductor Group – 2M x 32-Bit Dynamic RAM Module

HYM 322030S/GS-60/-70
2M × 32-Bit
Notes
1) All voltages are referenced to V_SS.
2) I_CC1, I_CC3, I_CC4 and I_CC6 depend on cycle rate.
3) I_CC1 and I_CC4 depend on output loading.
Specified values are measured with the output open.
4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles out of which at least one cycle
has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
5) V_IH (max) and V_IL (max) are reference levels for measuring timing of input signals.
Transition times are also measured between V_IH and V_IL.
6) Measured with a load equivalent of 2 TTL loads and 100 pF.
7) t_OFF (max) defines the time at which the output achieves the open-circuit condition and is not referenced to
output voltage levels.
8) Either t_RCH or t_RRH must be satisfied for a read cycle.
9) These parameters are referenced to the CAS leading edge.
10) t_WCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only.
If t_WCS > t_WCS (min), the cycle is an early write cycle and data out pin will remain open (high impedance).
11) Operation within the t_RCD (max) limit insures that t_RAC (max) can be met. t_RCD (max) is specified as a reference point
only. If t_RCD is greater than the specified t_RCD (max) limit, then access time is controlled by t_CAS.
12) Operation within the t_RAD (max) limit insures that t_RAC (max) can be met. t_RAD (max) is specified as a reference point
only. If t_RAD is greater than the specified t_RAD (max) limit, then access time is controlled by t_AA.
13) For CAS-before-RAS cycles only.
Semiconductor Group
569