HYM322030S Datasheet, PDF (7/9 Pages) Siemens Semiconductor Group – 2M x 32-Bit Dynamic RAM Module

HYM 322030S/GS-60/-70
2M × 32-Bit
AC Characteristics ^{4) 5)}
T_A = 0 to 70 ˚C, V_CC = 5 V ± 10 %, t_T = 5 ns
Parameter
Symbol
Limit Values
HYM
322030S/GS-60
HYM
322030S/GS-70
min.
max.
min.
max.
Random read or write cycle time t_RC
110
–
Fast page mode cycle time
t_PC
40
–
Access time from RAS
t ^{6) 11) 12)}
RAC
–
60
Access time from CAS
t ^{6) 11)}
CAC
–
15
Access time from column
t_AA
–
30
address
6) 12)
130
–
45
–
–
70
–
20
–
35
Access time from CAS
t_CPA
–
35
–
40
precharge
6)
CAS to output in low-Z
t 6)
CLZ
0
Output buffer turn-off delay
t 7)
OFF
0
Transition time (rise and fall)
t 5)
T
3
RAS precharge time
t_RP
40
RAS pulse width
t_RAS
60
RAS pulse width
(fast page mode)
t_RASP
60
–
0
20
0
50
3
–
50
10000 70
200000 70
–
20
50
–
10000
200000
CAS precharge to RAS delay
t_RHCP
35
RAS hold time
t_RSH
15
CAS hold time
t_CSH
60
CAS pulse width
t_CAS
15
RAS to CAS delay time
t 11)
RCD
20
RAS to column address
delay time
t_RAD
15
12)
–
40
–
20
–
70
10000 20
45
20
30
15
–
–
–
10000
50
35
CAS to RAS precharge time
t_CRP
5
–
CAS precharge time
(fast page mode)
t_CP
10
–
5
–
10
–
Row address setup time
t_ASR
0
–
Row address hold time
t_RAH
10
–
Column address setup time
t_ASC
0
–
Column address hold time
t_CAH
15
–
0
–
10
–
0
–
15
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Semiconductor Group
567