SDA5649 Datasheet, PDF (8/26 Pages) Siemens Semiconductor Group – Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder

SDA 5649
SDA 5649X
Data Transfer (Read Mode)
Step1: To start a data transfer the master generates a Start Condition on the bus by pulling the
SDA line low while the SCL line is held high. The byte address counter in the decoder is
reset and points to the first byte to be output.
Step 2: The bus master puts the chip address on the SDA line during the next eight SCL pulses.
Step 3: The master releases the SDA line during the ninth clock pulse. Thus the slave can generate
an acknowledge (AS) by pulling the SDA line to a low level. At this moment, the slave
switches to transmitting mode.
Step 4: During the next eight clock pulses the slave puts the addressed data byte onto the SDA
line.
Step 5: The reception of the byte is acknowledged by the master device which, in turn, pulls down
the SDA line during the next SCL clock pulse. By acknowledging a byte, the master
prompts the slave to increment its internal address counter and to provide the output of the
next data byte.
Step 6: Steps no. 4 and no. 5 are repeated, until the desired amount of bytes have been read.
Step 7: The last byte is output by the slave since it will not be acknowledged by the master.
Step 8: To conclude the read operation, the master doesn’t acknowledge the last byte to be
received. A No Acknowledge by the master (NAM) causes the slave to switch from
transmitting to receiving mode. Note that the master can prematurely cease any reading
operation by not acknowledging a byte.
Step 9: The master gains control over the SDA line and concludes the data transfer by generating
a Stop Condition on the bus, i. e., by producing a low/high transition on the SDA line while
the SCL line is in a high state. With the SDA and the SCL lines being both in a high state,
the I²C-Bus is free and ready for another data transfer to be started.
Semiconductor Group
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