SDA5649 Datasheet, PDF (7/26 Pages) Siemens Semiconductor Group – Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder

SDA 5649
SDA 5649X
Control Register
Bit Number
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
HDT PDC/ FOR1/
VPS FOR2
Default: All bits are set to 0 on power-up.
Bits 3 through 7 are used for test purposes and must not be changed for normal operation by user
software!
Bit 0: Determines, which kind of data is accessed via the I²C-Bus when PDC mode is active.
0
BDSP
8/ 30/ 2
data accessible
Value
1
BDSP 8/ 30/ 1 or
header row
data accessible (refer to description of Bit 2)
Bit 1: Determines the operating mode.
0
VPS mode active
Value
1
PDC mode active
Bit 2: Determines whether BDSP 8/30/1-data or header row data is accessible.
0
BDSP 8/30/1 data accessible
Value
1
Bytes no.38 through 45 of the header row
containing clock time accessible
Read Mode
For reading from the PDC decoder, the following format has to be used.
START Chipaddress Read Mode AS 1st Byte AM … Last Byte NAM
STOP
The contents of up to 13 registers (bytes) can be read starting with byte 1 bit 7 (refer to the table
Order of Data Output on the I²C-Bus and …) depending on the selected operating mode.
Semiconductor Group
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