HYS64V8000GU Datasheet, PDF (8/11 Pages) Siemens Semiconductor Group – 3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module

HYS64(72)V8000GU-10
8M x 64/72 SDRAM-Module
Parameter
Symbol Limit Values Unit
Activate(a) to Activate(b) Command t_RRD
period
CAS(a) to CAS(b) Command period t_CCD
Mode Register Set-up time
t_RSC
Power Down Mode Entry Time
t_SB
-10
min
max
20
–
1
–
20
–
0
10
ns 6
CLK
ns
ns
Refresh Cycle
Refresh Period
(4096 cycles)
Self Refresh Exit Time
t_REF
t_SREX
–
64
ms
10
Read Cycle
Data Out Hold Time
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
t_OH
3
–
ns
t_LZ
0
–
ns
t_HZ
3
10
ns 8
t_DQZ
2
–
CLK
Write Cycle
Write Recovery Time
CAS Latency = 3 _tWR
CAS Latency = 2
DQM Write Mask Latency
t_DQW
10
–
ns
15
–
ns
0
–
CLK
Semiconductor Group
8