HYS64V8000GU Datasheet, PDF (10/11 Pages) Siemens Semiconductor Group – 3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module

HYS64(72)V8000GU-10
8M x 64/72 SDRAM-Module
A serial presence detect storage device - E ²PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E ²PROM device during module
production using a serial presence detect protocol ( I ²C synchronous 2-wire bus)
SPD-Table:
Byte#
Description
SPD Entry Value Hex
x64 x72
-10 -10
0 Number of SPD bytes
128
80 80
1 Total bytes in Serial PD
256
08 08
2 Memory Type
SDRAM
04 04
3 Number of Row Addresses (without BS bits)
12
0C 0C
4 Number of Column Addresses (for x 8
SDRAM)
9
09 09
5 Number of DIMM Banks
1
01 01
6 Module Data Width
64 / 72
40 48
7 Module Data Width (contd’ )
0
00 00
8 Module Interface Levels
LVTTL
01 01
9 SDRAM Cycle Time at CL=3
10 ns
A0 A0
10 SDRAM Access time from Clock at CL=3
7.0 ns
70 70
11 Dimm Config (Error Det/Corr.)
none / ECC
00 02
12 Refresh Rate/Type
Self-Refresh, 15.6µs 80 80
13 SDRAM width, Primary
x8
08 08
14 Error Checking SDRAM data width
n/a / x8
00 08
15 Minimum clock delay for back-to-back ran-
dom column address
t_ccd = 1 CLK
01 01
16 Burst Length supported
1, 2, 4, 8 & full page 8F 8F
17 Number of internal SDRAM banks
4
04 04
18 Supported CAS Latencies
CAS latencies = 2,3 06 06
19 CS Latencies
CS latency = 0
01 01
20 WE Latencies
Write latency = 0
01 01
21 SDRAM DIMM module attributes
non buffered/non reg. 00 00
22 SDRAM Device Attributes :General
Vcc tol +/- 10%
06 06
23 SDRAM Cycle Time at CL = 2
15 ns
F0 F0
24 SDRAM Acces TIme from Clock at CL=2
8.0 ns
80 80
25 SDRAM Cycle Time at CL = 1
26 SDRAM Acces TIme from Clock at CL=1
27 Minimum Row Precharge Time
28 Minimum Row Active to Row Active delay
tRRD
not supported
not supported
30 ns
20 ns
FF FF
FF FF
1E 1E
14 14
Semiconductor Group
10