C541U Datasheet, PDF (53/63 Pages) Siemens Semiconductor Group – 8 BIT CMOS MICROCONTROLLER

C541U
Notes : Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid for the other
cases accordingly.
In the case of slave mode and CPHA=0, the output delay for the MSB applies to the falling edge
of SLS (if transmitter is enabled).
In the case of master mode and CPHA=0, the MSB becomes valid after the data has been written
into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition.
Figure 26
SSC Master Mode Timing
Semiconductor Group
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