C541U Datasheet, PDF (34/63 Pages) Siemens Semiconductor Group – 8 BIT CMOS MICROCONTROLLER

C541U
Fail Save Mechanisms
The C541U offers enhanced fail safe mechanisms, which allow an automatic recovery from
software upset or hardware failure :
– a programmable watchdog timer (WDT), with variable time-out period from 256 µs up to
approx. 0.55 µs at 12 MHz.
– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.
The watchdog timer in the C541U is a 15-bit timer, which is incremented by a count rate of f_OSC/12
or f_OSC/192. The system clock of the C541U is divided by two prescalers, a divide-by-two and a
divide-by-16 prescaler which are selected by bit WDTPSEL (WDTREL.7). For programming of the
watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 8-17
shows the block diagram of the watchdog timer unit.
f _OSC / 6
2
16
0
7
WDTL
WDT Reset-Request
WDCON (CO _H )
-
-
-
- OWDS WDTS WDT SWDT
Control Logic
External HW Reset
14
8
WDTH
WDTPSEL
76
0
WDTREL
MCB03384
Figure 17
Block Diagram of the Watchdog Timer
The watchdog timer can be started by software (bit SWDT) but it cannot be stopped during active
mode of the C541U. If the software fails to refresh the running watchdog timer an internal reset will
be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR
WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh sequence consists of
two consequtive instructions which set the bits WDT and SWDT each. The reset cause (external
reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted,
however, that the watchdog timer is halted during the idle mode and power down mode of the
processor.
Semiconductor Group
32