C541U Datasheet, PDF(46/63 Page) Siemens Semiconductor Group

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C541U Datasheet, PDF (46/63 Pages) Siemens Semiconductor Group – 8 BIT CMOS MICROCONTROLLER

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C541U

Power Supply Current

Parameter

Active mode

Idle mode

Power-down mode

12 MHz

Symbol

Limit Values

typ. 8)

max. 9)

IDD

IPD

Unit Test Condition

mA 4)

mA 5)

ÂµA VDD = 2â¦5.5 V 3)

Notes :

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these

pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise

pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,

or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD

specification when the address lines are stabilizing.

3) IPD (power-down mode) is measured under following conditions:

EA = Port 0 = VDD ; XTAL2 = N.C.; XTAL1 = VSS ; RESET = VSS; all other pins are disconnected.

the USB transceiver is switched off;

4) IDD (active mode) is measured with:

XTAL1 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VDD â 0.5 V; XTAL2 = N.C.;

EA = RESET = Port 0 = Port 1 = VDD ; all other pins are disconnected.

IDD would be slightly higher if a crystal oscillator is used (appr. 1 mA).

5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD â 0.5 V; XTAL2 = N.C.;

EA = RESET = Vss ; Port 0 = VDD ; all other pins are disconnected;

6) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified

operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input currents on all port

pins may not exceed 50 mA. The supply voltage VDD and VSS must remain within the specified limits.

7) Not 100% tested, guaranteed by design characterization.

8) The typical IDD values are periodically measured at TA = +25 Â°C but not 100% tested.

9) The maximum IDD values are measured under worst case conditions (TA = 0 Â°C and VDD = 5.5 V)

Semiconductor Group

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