C541U Datasheet, PDF (37/63 Pages) Siemens Semiconductor Group – 8 BIT CMOS MICROCONTROLLER

C541U
Power Saving Modes
The C541U provides two basic power saving modes, the idle mode and the power down mode.
– Idle mode
In the idle mode the main oscillator of the C541U continues to run, but the CPU is gated off
from the clock signal. However, the interrupt system, the SSC, the USB module, and the
timers with the exception of the watchdog timer are further provided with the clock. The CPU
status is preserved in its entirety : the stack pointer, program counter, program status word,
accumulator, and all other registers maintain their data during idle mode. The idle mode can
be terminated by activating any enabled interrupt. or by a hardware reset.
– Power down mode
In the power down mode, the RC osciillator and the on-chip oscillator which operates with the
XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the
contents of the on-chip RAM, XRAM and the SFR's are maintained. The power down mode
can be left either by an active reset signal or by a low signal at the P3.2/INT0 pin or any activity
on the USB bus. Using reset to leave power down mode puts the microcontroller with its SFRs
into the reset state. Using the INT0 pin or USB bus for power down mode exit maintains the
state of the SFRs, which has been frozen when power down mode is entered.
In the power down mode of operation, V_DD can be reduced to minimize power consumption. It must
be ensured, however, that V_DD is not reduced before the power down mode is invoked, and that V_DD
is restored to its normal operating level, before the power down mode is terminated. Table 7 gives
a general overview of the entry and exit procedures of the power saving modes.
Table 7
Power Saving Modes Overview
Mode
Idle mode
Entering
2-Instruction
Example
ORL PCON, #01H
ORL PCON, #20H
Power Down Mode ORL PCON, #02H
ORL PCON, #40H
Leaving by
Ocurrence of an
interrupt from a
peripheral unit
Hardware Reset
Hardware Reset
Short low pulse at
pin P3.2/INT0 or
activity on the USB
bus
Remarks
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
Semiconductor Group
35