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HYB5117805BSJ-50-60 Datasheet, PDF (5/23 Pages) Siemens Semiconductor Group – 2M x 8-Bit Dynamic RAM 2k Refresh
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter
Symbol Limit Values
min.
max.
Average VCC supply current
ICC1
-50 ns version
–
80
-60 ns version
–
70
(RAS, CAS, address cycling: tRC = tRC MIN.)
Standby VCC supply current (RAS = CAS = VIH) ICC2
–
2
Average VCC supply current, during RAS-only ICC3
refresh cycles
-50 ns version
–
80
-60 ns version
–
70
(RAS cycling, CAS = VIH, tRC = tRC MIN.)
Average VCC supply current, during hyper page ICC4
mode (EDO)
-50 ns version
–
35
-60 ns version
–
30
(RAS = VIL, CAS, address cycling: tPC = tPC MIN.)
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
–
1
Average VCC supply current, during CAS-
ICC6
before-RAS refresh mode
-50 ns version
–
80
-60 ns version
–
70
(RAS, CAS cycling: tRC = tRC MIN.)
Unit Test
Condition
mA 2, 3, )4
mA 2, 3, 4
mA –
mA 2, 4
mA 2, 4
mA 2, 3, 4
mA 2, 3, 4
mA 1
mA 2, 4
mA 2, 4
Capacitance
TA = 0 to 70 °C, VCC = 5 V ± 10 %, f = 1 MHz
Parameter
Input capacitance (A0 to A10)
Input capacitance (RAS, CAS, WE, OE)
I/O capacitance (I/O1 - I/O8)
Symbol
CI1
CI2
CIO
Limit Values
min.
max.
–
5
–
7
–
7
Unit
pF
pF
pF
Semiconductor Group
5
1998-10-01