SDA5650 Datasheet, PDF (25/41 Pages) Siemens Semiconductor Group – VPS / PDC-plus Decoder

SDA 5650/X
2.5 Description of DAVN and EHB Outputs
DAVN (Data Valid active low)
EHB (First Field active high)
Signal Output VPS Mode
PDC Mode
8/30/2 Mode 8/30/1 Mode Header Time
DAVN
H/L-transition
(set low)
L/H-transition
(set high)
always set high
in line 16 when in the line
valid VPS data is carrying
received
valid
8/30/2 data
in the line
carrying
valid
8/30/1 data
in the line
carrying
valid
header
row X/0 data
at the start of
line 16
at the beginning of the next field
i.e., at the start of the next data entry window
on power-up or during I²C-Bus accesses when the bus master
doesn’t acknowledge in order to generate the stop condition
EHB
L/H-transition
H/L-transition
at the beginning of the first field
at the beginning of the second field
In test mode (i.e. TI = high), both DAVN and EHB are controlled by the CS0 pin and
reproduce the state of the CS0 input.
Semiconductor Group
25
02.97