SDA5650 Datasheet, PDF (10/41 Pages) Siemens Semiconductor Group – VPS / PDC-plus Decoder

SDA 5650/X
2.2.2 Chip Address
There are two pairs of chip addresses, which are selected by the CS0-input pin
according to the following table:
CS0 Input
Low
High
Write Mode
20 (hex)
22 (hex)
Read Mode
21 (hex)
23 (hex)
2.2.3 Write Mode
For writing to the PDC decoder, the following format has to be used:
Start Chipaddress and Write Mode AS Byte to set Control Register AS Stop
Description of Data Transfer (Write Mode)
Step1: In order to start a data transfer the master generates a Start Condition on the
bus by pulling the SDA line low while the SCL line is held high.
Step 2: The bus master puts the chip address on the SDA line during the next eight
SCL pulses.
Step 3: The master releases the SDA line during the ninth clock pulse. Thus the slave
can generate an acknowledge (AS) by pulling the SDA line to a low level.
Step 4: The controller transmits the data byte to set the Control register
Step 5: The slave acknowledges the reception of the byte.
Step 6: The master concludes the data communication by generating a Stop
Condition.
The write mode is used to set the I²C-Bus control register which determines the
operating mode:
Semiconductor Group
10
02.97