SDA5650 Datasheet, PDF (18/41 Pages) Siemens Semiconductor Group – VPS / PDC-plus Decoder

SDA 5650/X
2.4 Order of Data Output on the I²C Bus and Bit Allocation for the Header
Time Mode (MAB=0) (cont’d)
I²C Bus
t
Byte 5 bit 7
6
5
4
3
2
1
0
Byte 6
bit 7
6
5
4
3
2
1
0
Byte 7
bit 7
6
5
4
3
2
1
0
Byte 8
bit 7
6
5
4
3
2
1
0
Header Time Mode
byte 42
bit 0²⁾
1
2
3
4
5
6
7
byte 43
bit 0
1
2
3
4
5
6
7
byte 44
bit 0
1
2
3
4
5
6
7
byte 45
bit 0
1
2
3
4
5
6
7
1) _{Message bit numbers according to EBU specification of PDC system.}
2) _{Transmission bit number.}
Semiconductor Group
18
02.97