HYB514405BJ Datasheet, PDF (25/25 Pages) Siemens Semiconductor Group – 1M x 4-Bit Dynamic RAM

HYB 514405BJ/BJL-50/-60/-70
1M x 4 EDO - DRAM
Test Mode
As the HYB 514405BJ/BT is organized internally as 512K x 8-bits, a test mode cycle using 8:1
compression can be used to improve test time. Note that in the 1M x 4 version the test time is
reduced by 1/2 for a linear test pattern.
In a test mode “write” the data from each I/O1 pin is written into eight bits simultaneously (all “1” s
or all “0” s).The I/O2-I/O4 inputs are not used for writing in test mode. In test mode “read” each I/O
output is used for indicating the test mode result. If the internal eight bits are equal, the I/O would
indicate a “1”. If they were not equal, the I/O would indicate a “0”.Note that in test mode „read“ I/O1-
I/O3 are always driven to „ones“ ,i.e. all outputs will be „1“s for a test mode „pass“. The WCBR cycle
(WE, CAS before RAS) puts the device into test mode. To exit from test mode, a “CAS before RAS
refresh”, “RAS only refresh” or “Hidden refresh” can be used.
Addresses A10R, A10C and A0C are don‘t care during test mode.
Package Outlines
P-SOJ-26/20-5
(Small Outline J-Leaded Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
25
Dimensions in mm