SDA9362 Datasheet, PDF (23/39 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9362
HSYNC
12
14 15 16 17 18 19 20 21 22 23 24 25
VSYNC
1 Line
Start of odd Field
Start of even Field
VD-
VBL
(BSE = 0)
VBL
(BSE = 1,
VBT = 16)
VBL
(BSE = 1,
VBT = 25)
VBL
(BSE = 1,
VBT = 26)
2 Lines
3 Lines
A
21 Lines
16 Lines
25 Lines
26 Lines
2 Lines
UED10261
Figure 4
Vertical Blanking Pulse VBL when STE = 0 and Number of Lines per Field = Constant
Semiconductor Group
23
1998-02-01