SDA9362 Datasheet, PDF (11/39 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9362
VPROT:
Vertical sawtooth voltage
V_i < V1 in first half of V-period or
V_i > V2 in second half: HD disabled
The pin SCP delivers the composite blanking signal SCP. It contains burst (V_b), H-
blanking HBL (V_HBL) and selectable V-blanking (control bit SSC). The phase of the H-
blanking period can be varied by Ι²C Bus. For the timing following settings are possible:
BD = 1
BD = 0, BSE = 0 (default value)
BD = 0, BSE = 1(alignment range)
SSC = 0
SSC = 1
: t_BL = 0
: t_HBL = t_f (H-flyback time)
: t_HBL = (4 _* H-blanking-time + 1) / CLL
: t_DBL = (H-shift + 4 _* H-blanking-phase
-2 _* H-blanking-time + 43) / CLL
: t_BL = t_VBL during V-blanking period
: t_BL is always t_HBL
Input Signal
HSYNC
V_OH
V_OHBL
V_OL
t _DB
t _DBL
t_B
t _BL
UED10260
Figure 3
BG-pulse width t_B
Delay to HSYNC t_DB
54 / CLL
36 / CLL
Semiconductor Group
11
1998-02-01