SDA9362 Datasheet, PDF (13/39 Pages) Siemens Semiconductor Group – DDC-PLUS-Deflection Controller

SDA 9362
2.3 Reset Modes
The circuit is only completely reset at power-on/off (timing diagram refer 5.3). If the pin
RESN has L-level or during standby operation some parts of the circuit are not affected
(timing diagram refer 5.4):
Power-On-Reset External Reset
(pin RESN=0)
Standby Mode
(I²C-Bit STDBY=1)
HD output
High
Active
Active
H-protection
V-protection
Ι²C Interface (SDA,
SCL)
Ι²C Register
01_H..1B_H
Ι²C Register
00_H, 48_H
Status bit PONRES
Inactive
Inactive
Tristate
Active
Active¹⁾
Ready
Active
Active¹⁾
Ready
Set to default values Set to default values Set to default values
Set to default values Not affected
Set to 1²⁾
Set to 1
Not affected
Not affected
V_REFP
V_REFH, V_REFL
CPU
Not affected
Not affected
Inactive
Not affected
Not affected
Inactive
Not affected
Inactive
Inactive
1) _{Inactive if HPROT < V2 (typ. 2.4 V)}
2) _{Can only be read after Power-On-Reset is finished}
Note: Power-On-Reset state is deactivated after ca. 32 cycles of the X1/X2 oscillator
clock. RESN = Low and standby state are deactivated after ca. 42 cycles of the
CLL clock.
2.4 Frequency Ranges
H
31.25 kHz
31.5 kHz
V
50 Hz
100 Hz
60 Hz
120 Hz
n_L
625 NI / 1250I
625 I
525 NI / 1050 I
525 I
The allowed deviation of all input line frequencies is max. ± 4.5 %.
n_L: Number of lines per frame
I: Interlaced
NI: Non interlaced
Semiconductor Group
13
1998-02-01