SLX24C01 Datasheet, PDF (20/27 Pages) Siemens Semiconductor Group – 1/2 Kbit 128/256 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

SLx 24C01/02/P
7.2 Protection Bit Write and Erase
For writing or erasing a protection bit, the data of the respective page have to be known
by the master. The data of the page are not affected by the write or erase procedure of
the protection bit. The I²C-Bus protocol is shown in figure 15 for protection bit write and
figure 16 for protection bit erase.
Bus Activity
Master
S
T
A
Command
Byte
R _CSW
T
EEPROM
Address
EEA n
S
T
A
Command
Byte
R _CSW
T
Control
Byte
CTW
Data
Byte n
Data ... Data
Byte n+1 Byte n+7
S
T
O
P
SDA Line S
0
0000 S
0
01
P
Bus Activity
EEPROM
A
A
C
C
K
K
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
IED02142
Figure 15
Sequence for Protection Bit Write
Bus Activity
Master
S
T
A
Command
Byte
R _CSW
T
EEPROM
Address
EEA n
S
T
A
Command
Byte
R _CSW
T
Control
Byte
CTE
Data
Byte n
Data ... Data
Byte n+1 Byte n+7
S
T
O
P
SDA Line S
0
0000 S
0
11
P
Bus Activity
EEPROM
A
A
C
C
K
K
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
IED02143
Figure 16
Sequence for Protection Bit Erase
The first command byte CSW followed by the control byte EEA addresses the page to
be protected. The second command byte CSW (identical content of first CSW) is
followed by the control byte CTW = 01_H for protection bit write or CTE = 03_H for protection
bit erase. Depending on CTx, the addressed protection bit will be either written or
erased.
Semiconductor Group
20
1998-07-27