SLX24C01 Datasheet, PDF (12/27 Pages) Siemens Semiconductor Group – 1/2 Kbit 128/256 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

SLx 24C01/02/P
5.2 Page Write
Address Setting
Transmission of Data
Programming Cycle
The page write procedure is the same as the byte write
procedure up to the first data byte. In a page write instruction
however, entry of the EEPROM address byte EEA is followed
by a sequence of one to maximum eight data bytes with the
new data to be programmed. These bytes are transferred to
the internal page buffer of the EEPROM.
The first entered data byte will be stored according to the
EEPROM address n given by EEA (A0 to A6 or A7). The
internal address counter is incremented automatically after the
entered data byte has been acknowledged. The next data byte
is then stored at the next higher EEPROM address. EEPROM
addresses within the same page have common page address
bits A2 through A6 or A7. Only the respective three least
significant address bits A0 through A2 are incremented, as all
data bytes to be programmed simultaneously have to be
within the same page.
The master stops data entry by applying a STOP condition,
which also starts the internally timed erase/write cycle. In the
first step, all selected bytes are erased to “1”. With the next
internal step, the addressed bytes are written according to the
contents of the page buffer.
Those bytes of the page that have not been addressed are not included in the
programming.
Bus Activity
Master
S
T
A _{Command Byte EEPROM Address}
R
CSW
EEA n
T
Data Byte n
S
Data Byte n+1 Data Byte n+7 ^T
O
P
SDA Line S
0
P
Bus Activity
EEPROM
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
IED02280
Figure 8
Page Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3 Acknowledge Polling).
Semiconductor Group
12
1998-07-27