SLX24C01 Datasheet, PDF (11/27 Pages) Siemens Semiconductor Group – 1/2 Kbit 128/256 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

SLx 24C01/02/P
5
Write Operations
Changing of the EEPROM data is initiated by the master with the command byte CSW.
Depending on the state of the Write Protection pin WP and of the Protection Bits (refer
to chapter 7 Page Protection Mode^TM) either one byte (Byte Write) or up to 8 bytes
(Page Write) are modified in one programming procedure.
5.1 Byte Write
Address Setting
Transmission of Data
Programming Cycle
After a START condition the master transmits the Chip Select
Write byte CSW. The EEPROM acknowledges the CSW byte
during the ninth clock cycle. The following byte with the
EEPROM address (A0 to A6 or A7) is loaded into the address
counter of the EEPROM and acknowledged by the EEPROM.
Finally the master transmits the data byte which is also
acknowledged by the EEPROM into the internal buffer.
Then the master applies a STOP condition which starts the
internal programming procedure. The data bytes are written in
the memory location addressed in the EEA byte (A0 to A6 or
A7). The programming procedure consists of an internally
timed erase/write cycle. In the first step, the selected byte is
erased to “1”. With the next internal step, the addressed byte
is written according to the contents of the buffer.
S
T
S
Bus Activity ^A Command Byte EEPROM Address Data Byte
T
Master
R
CSW
EEA
O
T
P
SDA Line S
0
A
Bus Activity
C
EEPROM
K
P
A
A
C
C
K
K
IED02129
Figure 7
Byte Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3 Acknowledge Polling).
Semiconductor Group
11
1998-07-27