HYB3164160AT Datasheet, PDF (2/26 Pages) Siemens Semiconductor Group – 4M x 16-Bit Dynamic RAM

HYB3164(5/6)160AT(L)-40/-50/-60
4M x 16-DRAM
This device is a 64 MBit dynamic RAM organized 4 194 304 by 16 bits. The device is fabricated on
an advanced second generation 64Mbit 0,35µm-CMOS silicon gate process technology. The circuit
and process design allow this device to achieve high performance and low power dissipation. This
DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or
LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)160AT to be packaged in a 400
mil wide TSOP-50 package. These packages provide high system bit densities and are compatible
with commonly used automatic testing and insertion equipment. The HYB3164(5/6)160ATL parts
(L-version) have a very low power „sleep mode“ supported by Self Refresh.
Ordering Information
Type
8k-refresh versions:
HYB 3164160AT-40
HYB 3164160AT-50
HYB 3164160AT-60
HYB 3164160ATL-50
HYB 3164160ATL-60
4k-refresh versions:
HYB 3165160AT-40
HYB 3165160AT-50
HYB 3165160AT-60
HYB 3165160ATL-50
HYB 3165160ATL-60
2k-refresh versions:
HYB 3166160AT-40
HYB 3166160AT-50
HYB 3166160AT-60
HYB 3166160ATL-50
HYB 3166160ATL-60
Ordering
Code
Package
Descriptions
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
400 mil
400 mil
400 mil
400 mil
400 mil
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
400 mil
400 mil
400 mil
400 mil
400 mil
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
P-TSOPII-50
400 mil
400 mil
400 mil
400 mil
400 mil
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
Semiconductor Group
2