LRS1383 Datasheet, PDF (89/114 Pages) Sharp Electrionic Components – STACKED CHIP 32M FLASH AND 8M SRAM

FUM00701
43
Bus
Operation
Command
Comments
Write
<First cycle>
Data=60H
Addr=Within Block to be
Set Block _{Locked or Locked-down}
Lock Bit/Set
Block Lock- ^{<Second cycle>}
down Bit ^{Data= 01H (Lock Bit), or}
2FH(Lock-down Bit)
Addr=Within Block to be
Locked or Locked-down
Read
Status Register Data
Addr=Within Partition
Standby
Check SR.4, 5
Both 1=Command Sequence
Error
Write
Read
ID
Code
Data=90H
Addr=Within
Partition
Read
Lock Bit or Lock-down Bit
Data
Addr=Block Address+2
(see Table 6 through
Table 8)
Standby
Check DQ₀/DQ₁
1=Lock Bit or Lock-down
Bit is Set
Repeat for the subsequent set block lock/lock-down bit.
Lock status check can be done after each set block lock/
lock-down bit operation or after a sequence of set block
lock/lock-down bit operations.
SR.5 and SR.4 are only cleared by the Clear Status
Register command in cases where multiple block lock/
lock-down bits are set before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Write FFH after a sequence of set block lock/lock-down
bit operations to place device in read array mode.
Bus
Operation
Command
Comments
Write
Read Status Data=70H
Register Addr=Within Partition
Read
Status Register Data
Addr=Within Partition
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Figure 11. Set Block Lock Bit and Set Block Lock-down Bit Flowchart
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20