LRS1383 Datasheet, PDF (72/114 Pages) Sharp Electrionic Components – STACKED CHIP 32M FLASH AND 8M SRAM

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4.6 Block Erase Command
The two-cycle Block Erase command initiates one block
erase at the addressed block within the target partition.
Read operations to that partition output the status register
data of its partition. At the first cycle, command (20H)
and an address within the block to be erased is written to
the CUI, and command (D0H) and the same address as
the first cycle is written at the second cycle. Once the
Block Erase command is successfully written, the WSM
automatically starts erase and verification processes. The
data in the selected block are erased (becomes FFFFH).
The system CPU can detect the block erase completion by
analyzing the output data of the status register bit SR.7.
The partition including the block to be erased remains in
read status register mode after the completion of the block
erase operation until another command is written to the
CUI. Figure 5.1 and Figure 5.2 show a flowchart of the
block erase operation.
Check the status register bit SR.5 at the end of block
erase. If a block erase error is detected, the status register
should be cleared before system software attempts
corrective actions. The partition remains in read status
register mode until a new command is written to that
partition.
This two-cycle command sequence ensures that block
contents are not accidentally erased. An invalid Block
Erase command sequence will result in status register bits
SR.5 and SR.4 of the partition being set to "1" and the
operation will be aborted.
For reliable block erase operation, apply the specified
voltage on V_CC and V_PPH1/2 on V_PP. In the absence of this
voltage, block erase operations are not guaranteed. For
example, attempting a block erase at V_PP V_PPLK causes
SR.5 and SR.3 being set to "1". Also, successful block
erase requires that the selected block is unlocked. When
block erase is attempted to the locked block, bits SR.5
and SR.1 will be set to "1".
Block erase operation may occur in only one partition at a
time. Other partitions must be in one of the read modes.
4.7 Full Chip Erase Command
The two-cycle Full Chip Erase command erases all of the
unlocked blocks. Before writing this command, all of the
partitions should be ready (WSM should not be occupied
by any partition). At the first cycle, command (30H) is
written to the CUI, and command (D0H) is written at the
second cycle. After writing the command, the device
outputs the status register data when any address within
the device is selected. The WSM automatically starts the
erase operation for all unlocked blocks, skipping the
locked blocks. The full chip erase operation cannot be
suspended through the erase suspend command
(described later). The system CPU can detect the full chip
erase completion by analyzing the output data of the
status register bit SR.7. All the partitions remain in the
read status register mode after the completion of the full
chip erase operation until another command is written to
the CUI. Figure 6.1 and Figure 6.2 show a flowchart of
the full chip erase operation.
The WSM aborts the operation upon encountering an
error during the full chip erase operation and leaves the
remaining blocks not erased. After the full chip erase
operation, check the status register bit SR.5. When a full
chip erase error is detected, SR5 of all partitions will be
set to "1". The status registers for all partitions should be
cleared before system software attempts corrective
actions. After that, retry the Full Chip Erase command or
erase block by block using the Block Erase command.
This two-cycle command sequence ensures that block
contents are not accidentally erased. An invalid Full Chip
Erase command sequence will result in status register bits
SR.5 and SR.4 of all partitions being set to "1" and the
operation will be aborted.
For reliable full chip erase operation, apply the specified
voltage on V_CC and V_PPH1/2 on V_PP. In the absence of this
voltage, full chip erase operations are not guaranteed. For
example, attempting a full chip erase at V_PP V_PPLK
causes SR.5 and SR.3 being set to "1".
As previously mentioned, the Full Chip Erase command
erases all blocks except for the locked blocks. Unlike the
block erase, the status register bits SR.5 and SR.1 are not
set to "1" even if the locked block is included. However,
when all blocks are locked, the bits SR.5 and SR.1 are set
to "1" and the operation will not be executed.
If an error is detected during the full chip erase operation,
error bits for all status registers are set to "1". This
requires that the Clear Status Register command be
written to all partitions to clear the error bits.
Dual work operation is not available during the full chip
erase mode. The memory array data cannot be read in this
mode. To return to the read array mode, write the Read
Array command (FFH) to the CUI after the completion of
the full chip erase operation.
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20