LRS1383 Datasheet, PDF (28/114 Pages) Sharp Electrionic Components – STACKED CHIP 32M FLASH AND 8M SRAM

LRS1383
26
12.6 Reset Operations^(1,2)
Symbol
Parameter
(T_A = -25°C to +85°C, F-V_CC = 2.7V to 3.3V)
Notes
Min.
Max.
Unit
t_PLPH
F-RST Low to Reset during Read
(F-RST should be low during power-up.)
1, 2, 3
100
ns
t_PLRH F-RST Low to Reset during Erase or Program
1, 3, 4
22
s
t_VPH F-V_CC 2.7V to F-RST High
1, 3, 5
100
ns
t_VHQV F-V_CC 2.7V to Output Delay
3
1
ms
Notes:
1. A reset time, t_PHQV, is required from the later of SR.7 (F-RY/BY) going "1" (High-Z) or F-RST going high until outputs
are valid. See the AC Characteristics - read cycle for t_PHQV.
2. t_PLPH is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If F-RST asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,
the reset will complete within 100ns.
5. When the device power-up, holding F-RST low minimum 100ns is required after F-V_CC has been in predefined range and
also has been in stable there.
AC Waveform for Reset Operation