ID246 Datasheet, PDF (8/38 Pages) Sharp Electrionic Components – Flash Memory Card

SHARI=
ID246 SERIES PRODUCT OVERVIEW
7
6. Functions
6.1 Common Memory
6. 1. 1 Common Memory Architecture
Figure 2 shows common memory architecture of ID246 series flash memory card. Device pair is consisted of two
pieces of flash memory devices. Each device has individually erasable and lockable blocks. All blocks are divided
into odd bytes and even bytes.
Each device pair and block is selected by address bits. Table 3 shows definitions of address bits.
DEVICE PAIR 5
DEVll
1 DEVIO
=
=
=
DEVICi PAIR 2
DEVS
1 DEV4
DEVIti PAIR 1
DEV3
1 DEV2
I
DEVICE PAIR 0
LH28FO32SKD LH28FO32SKD
- jGx-8&-
- - -4;I z 8jjii
DEVl
DEVO
//
Bank1
-
Bank0
/’ Blodc63
/
/1
I
/
I
I
‘‘WI
‘I
I
I
1I
Bank1
Bank0
1
ODD
EVEN
Word Mode
Odd-Byte Mode
I\1
D15-D8
yte Mode
Word Mode
Byte Mode
D7-DO
F1076E4)’
Figure 2. Common Memory Architecture
Table 3. Address Difinitions
Address Pifinitions
Select Even / Odd byte in the byte access
mode.
Select address in the block.
Select a block.
Select a bank
Select a device pair.
32MB ,4OMB ,48MB
A0
A16-Al (64KJ3/Block)
A21 -A17 (32blocks/bank)
A22 (2banks/device)
A25 -A23
T1173E-01