ID246 Datasheet, PDF (17/38 Pages) Sharp Electrionic Components – Flash Memory Card

SHARP
ID246 SERIES PRODUCT OVERVIEW
16
9. 5 Write Protection Register (Address:41 04h)
Address
4104h
Bit.7
Bit.6
Bit.5
Bit.4
Bit.3
Bit.2
Bit. 1
Reserved
BLKEN
CMWP
BLKEN:
CMWP:
CISWP:
Block Locking Enable
1 = Enable Block Locking 0 = All Block Unlocked
Common Memory Write Protect
1 = Common Memory without CIS region in Write Protect Status
Common Memory CIS Write Protect
1 = Common Memory CIS in Write Protect Status
Bit.0
CISWP
TI 176E4l
9. 6 Sleep Control Register (Address:41 18h-411 Ah)
Address
Bit.7
Bit.6
Bit.5
Bit.4
Bit.3
Bit.2
Bit. 1
Bit.0
411Al-l
Reserved
4118h
Reserved
DEV 10/l 1 DEV8/9 DEV6/7 DEV4/5 DEV2J3 DEVO/l
l= Select sleep mode device-pair
If set to “I”, the corresponding device-pairs are putted into deep powerdown
by PWDN bit of Configuration Status Register.
mode
TIW741
9. 7 Ready/Busy
Address
4122h
4120h
Mask Register (Address:41 20h-4122h)
Bit.7
DEV7
Bit.6
Bit.5
Bit.4
Bit.3
Bit.2
Bit.1
Bit.0
Reserved
DEVll
DEVlO
DEV9
DEV8
DEV6
DEVS 1 DEV4
DEV3
DEV2
DEVl
DEVO
1 =Mask the Rdy/Bsy#
The corresponding device’s Rdy/Bsy# signals to set bit are ignored for cards
RDY/BSY# output.
9. 8 Ready/Busy
Address
413231
4130h
Status Register (Address:41 30h-4132h)
Bit.7
Bit.6
Bit.5
Bit.4
Bit.3
Bit.2
Reserved
DEVI 1 DEVIO
DEV7
DEV6
DEVS
DEV4
DEV3
DEV2
l=READY
O=BUSY
Each bit indicates the corresponding device’s Rdy/Bsy# signal.
Bit. 1
DEV9
DEVl
Bit.0
DEV8
DEVO
TlOIlOl
9.9 Ready/Busy Mode Register (Address:41 40h)
Address
Bit.7
Bit.6
Bit.5
Bit.4
Bit.3
Bit.2
Bit.1
Bit.0
4140h
RACK:
MODE:
Reserved
RACK
MODE
Ready Acknowledge Bit
Must clear this bit after receiving ready status to prepare for next device’s ready
transition.
RDY/BSY# Mode
1 = High-Performance Mode 0 = PCMCIA Mode
TIMSOL